1. Design a mod-6 Ring counter using J-K flip-flops.
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- Problem Statement: You design a circuit of a decade counter that will count from 0-9 only. You will only be using the following: (a) Button – only 1 button will be used to trigger the counting. (b) Flip flop IC to used as counting circuit with 4 - BITS binary OUTPUT. (c) IC's for Decoding the Binary OUTPUT of Flip-flops to Decimal Output (d) 7- Segment Display to display the OUTPUT from 0-9. Block Diagram: 4 Bit Binary Flip-Flop 7-Segment Display Button Decoder Circuits CircuitsDesign 1-5 count-up Counters using JK Flip-Flops. 001-010- 011-100- 101- back to 001 03 Required: a) Excitation of Flip-Flop b) State diagram and circuit excitation table. c) Obtain simplified equations using k-map. d) Design logic diagram.Design a 6-bit counter with control input using flip-flops. Every hour pulseIt should be a design that will increase or decrease by 4 when it arrives. Control input increment orwill determine the decrease. Increasing when control input is 0, decreasing when 1should be designed.
- Design a shift register using d flip flop and logic gates to go from 0001 to 0010 to 0100 to 1000 and repeatingConstruct an asynchronous counter with a modulus of eleven by using J-K flip-flops. The counter should follow the straight binary sequence from 0000 through 1011.Design a 3-bit Shift Left register using D flip-flop. Draw the logic diagram of a 3-bit Shift left register .
- show the waveforms for each flip-flop output with respect For the ring counter in Figure to the clock. Assume that FF0 is initially SET and that the rest are RESET. Show at least ten clock pulses. D D. FFO FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 FP9 CLKHow a 0-9 Encoder works using 7 segments using flip flops.1. Design a 4-bit synchronous down-counter using T flip-flops. i. Write a "function table" showing current and next values for each count, and the T input values. ii. Give the Boolean functions for each T input. iii. Draw the logic network; label all inputs and outputs.
- 1-Design a 4-bit ripple up counter using positive edge trigger J-K flip-flops.2- Design a 4-bit shift left register using D flip-flops.3- Design a 3-bit shift right register using D flip-flops.4- Draw a 4-bit shift right register using D flip flops. Show the contents of the register after three times shift right with serial input (101). Assume the register initially contains (1100)Design a 4-bit arithmetic circuit, with two selection variables S1 and S0, that generates the arithmetic operations in the following table. Draw the logic diagram for a single bit stage. Note that B’ represents “Not B”. Draw the logic diagram for a single bit staga) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)